At Zetta, we're building the next NVIDIA. Our novel polymorphic chips are a generation ahead of anything on the market. We're essentially building the substrate that will power all future knowledge and scientific discovery.

Our XPU chips are state-of-the-art AI compute engines capable of reconfiguring themselves to optimize the dataflow of each model (training & inference!) to be fast and efficient enough to support AGI, and eventually ASI, without requiring massive power infrastructure. Through our novel polymorphic architecture, we're achieving unprecedented performance gains over current SOTA GPUs while dramatically reducing energy consumption.

The team consists of exceptional engineers obsessed with pushing the boundaries of what's possible in computing and AI, and we're now seeking our next technical member!

• Ready to go all-in and do the work of your life
• Willing to be hardcore when pushing technical boundaries
• A technical Powerhouse who loves working across the hardware-software boundary
• Deeply passionate and obsessed with computing and AI
• Hungry to build something that actually matters

• Background in Electrical Engineering, Computer Engineering, or equivalent field
• Owned major RTL-to-GDSII steps (floorplanning, power planning, placement, CTS, routing, ECOs, timing closure)
• Strong foundation in mixed-signal & digital IC design (VLSI, semiconductor physics, RTL)
• Strong signoff fundamentals (STA setup/hold across corners, RC extraction, DRC/LVS/antenna/erc closure, tapeout readiness)
• Proficiency with industry EDA flows/tools (Innovus/ICC2, PrimeTime, StarRC/Quantus, Calibre, OpenROAD)
• Constraint and methodology expertise (SDC authoring/validation, MMMC setup, clocking strategy, clean handoffs with RTL)
• Power integrity expertise (IR/EM analysis, power grid planning, practical mitigation tradeoffs)
• Debug expertise (congestion/timing pathologies, routing-driven timing, crosstalk sensitivity, SI/PI interactions)
• EDA flow automation and scripting (Tcl, Python, Nix)

• 5 years (or equivalent) hands-on digital/SoC physical design, with 1 successful tapeout (ideally 7nm or smaller)
• Advanced-node signoff experience (=5nm) and modern variation methodology (OCV/AOCV, PVT/derates) with strong correlation discipline
• Top-level integration experience across hierarchical blocks (abstracts, boundary timing, physical integration, chip-level routing strategy)
• Experience with (Sci)ML frameworks (eg, PyTorch/TinyGrad/JAX/Lux.jl)
• Experience with systems programming (Linux Kernel modules, low-level)
• Autodidactic polymath with a strong mathematical background
• Someone who doesn't fret when faced with near-impossible technical challenges

• Be one of the first employees shaping a revolutionary technology
• Work directly with the founding team of exceptional engineers at our San Francisco HQ
• Own critical decisions that will influence the future of AI compute
• Grow into a technical leader as we scale
• Highly competitive compensation significant equity

This is THE chance to do the work of your life. The chance to build something that will be remembered. To go hardcore on a technical moonshot that will actually matter for over 100 to 1,000 years.