Overview
LeadStack Inc. is an award winning, one of the nation's fastest growing, certified minority owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.
Position
Design Verification Engineer (GPU) -W2 only
Duration
Duration: 7+ months
Location
Location: Onsite, 5 days a week in San Jose, CA
Compensation
PR: $75/hr - $95/hr on W2
Vertical
Vertical: Technical
Description
As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.
Responsibilities
- Work with architects and designers to build verification environments and test plans
- Craft functional verification coverage strategy to ensure complete test suite implementation
- Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
- Analyze failing tests to root cause along, working with RTL and reference modeling teams
- Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
- Examine code coverage results, identifying exclusions and improving stimulus
- Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics
Qualifications
- BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
- Proficient in System Verilog/UVM/OVM, and OOP/C+
- Deep understanding of constrained randomization and the development of efficient test suites
- Experience with code coverage and functional coverage-driven verification methodology.
- Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench
- Working knowledge of Scripting languages such as Python or Perl
- Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines
Preferred qualifications
- MS CE/EE with 5+ years of industry experience in verification
- Good verbal and written communication skills
- Experience of GPU or CPU is a plus
know more about current opportunities at LeadStack, please visit us on https://leadstackinc.com/careers/
Should you have any questions, feel free to call me on (513) 3184502 or send an email on (see below)

San Jose, CA, United States of America
$75/hr - $95/hr
Click apply
JS26489_25303_77D230491EAC3A8FF1240A14B13DBA1E
24/01/2026 18:17:27
We strongly recommend that you should never provide your bank account details to an advertiser during the job application process. Should you receive a request of this nature
please contact support giving the advertiser's name and job reference.